1. Field of the Invention
The present invention relates to a memory control circuit for controlling a plurality of memories corresponding to a plurality of logic interfaces, respectively.
2. Description of the Background Art
A controller incorporating a CPU (central processing unit) usually requires two kinds of memories: nonvolatile memories such as a ROM (Read Only Memory) for storing an activation program, initial data and the like and a flash memory (hereinafter, referred to as xe2x80x9cboot memoryxe2x80x9d), and volatile RAMs (Random Access Memory) used for storage of loaded programs and temporary storage of variables. The controller and these memories are interconnected via a bus, and as a logic interface standard for connecting these controller and memories, TTL (Transistorxe2x80x94Transistor Logic) and LVTTL (Low-Voltage TTL), SSTL (Stub Series Terminated Logic), LS-TTL (Low power Schottky-TTL) and the like are employed.
Each memory has an input/output interface (level shifter) for converting an input voltage into an internal voltage and converting the internal voltage into an output voltage according to the logic interface. For example, according to the LVTTL standard defined by the standardization organism JEDEC (Joint Electron Device Engineering Council), with respect to a source voltage VDD, input voltages that are determined as xe2x80x9chigh levelxe2x80x9d (VIH) are defined in the range of 2 V (volts) to VDD+0.3 V (volts), input voltages that are determined as xe2x80x9clow levelxe2x80x9d (VIL) are defined in the range of xe2x88x920.3 V (volts) to +0.8 V (volts), and values in the vicinity of 3.3 V are recommended as the value of the source voltage VDD. Also according to the LVTLL standard, the minimum value of high level output voltages (VOH) is defined as 2.4 V, and the maximum value of low level output voltages (VOH) is defined as 0.4 V.
In the case where the above-mentioned boot memory and the RAM use the same logic interface, a bus can be shared for transmitting address signals, control signals and data signals without any problems. However, if such a bus is shared in the condition that these memories use different logic interfaces and thus the source voltages VDD are different, a voltage higher than the input withstand pressure is applied to a memory supporting lower source voltage, causing a latch-up and the like, which triggers a breakdown in the input/output interface, instability of operation of the memory and the like problems. In order to avoid such problems, the bus wiring can be arranged individually and separately for each of the memories using different source voltages VDD.
FIG. 13 is a schematic view showing one example of a memory control circuit adopting separate bus wiring for individual memories. This memory control circuit includes a controller 1001 incorporating a CPU 101, a boot memory 115 implemented by a nonvolatile memory, and a RAM 114. The source voltage VDD of the RAM 114 is 2.5 V, the source voltage VDD of the boot memory 115 is 3.3 V, and these memories adopt different source voltages.
Between the controller 1001 and the RAM 114 a first control bus 110 for transmitting address signals and control signals to the RAM 114 and a first data bus 111 for transmitting data signals are disposed, and between the controller 1001 and the boot memory 115 a second control bus 112 which is separate from the control bus 110 and a second data bus 113 which is separate from the data bus 111 are disposed.
The controller 1001 is equipped with a MIU (memory interface) 102 for performing memory management with respect to the RAM 114 and the nonvolatile memory 115. The CPU 101 first issues an access request with respect to the MIU 102 when accessing to the RAM 114 or the nonvolatile memory 115. After approving the access request, the MIU 102 fetches an address signal AD0 and a control signal CT0 transmitted from the CPU 101 and outputs these signals as an address signal ADin and a control signal CTin in predetermined timing.
Also the controller 100, is equipped with a PAD circuit 105 supporting a logic interface of the RAM 114 and a PAD circuit 106 supporting a logic interface of the nonvolatile memory 115.
The PAD circuit 105 supporting the low voltage standard of the RAM 114 has two level converters 105A and 105B for converting voltage level of input signal. In accessing and writing to the RAM 114, the level converter 105A converts the voltage levels of an address signal ADin and a control signal CTin inputted from the memory controller 103 and outputs signals after conversion to the control bus 110 via an output port 107A for supplying to the RAM 114. Also write data DO output from the CPU 101 is converted into data RD at the level converter 105B and transferred via the data bus 111 from an input/output port 107B to the RAM 114 to be written therein. On the other hand, in accessing the RAM 114 for reading, a data signal read from the RAM 114 is transferred via the data bus 111 to be inputted to the input/output port 107B, and converted at the level converter 105B into data RDin and inputted to the xe2x80x9c1xe2x80x9d side terminal of the selector 104. At this time, the memory controller 103 supplies the selector 104 with a selection signal of high level. In response to this selection signal, the selector 104 selects the data RDin and outputs it as readout data DI to the CPU 101.
On the other hand, the PAD circuit 106 which supports the high voltage standard of the nonvolatile memory 115 has two level converters 106A and 106B. When accessing the nonvolatile memory 115 for reading, the level converter 106A converts the voltage levels of an address signal ADin and a control signal CTin inputted from the memory controller 103 and outputs signals after conversion to the control bus 112 via an output port 107C for supplying to the nonvolatile memory 115. Then a data signal read out from the nonvolatile memory 115 is transferred to an input port 107D via the data bus 113 and converted to data NVDin at the level converter 106B to be inputted to the xe2x80x9c0xe2x80x9d side terminal of the selector 104. At this time, since the memory controller 103 supplies the selector 104 with a selection signal of low level, the selector 104 selects data NVDin in response to that selection signal, and outputs it to the CPU 101 as readout data DI.
In the above-described memory control circuit shown in FIG. 13, it is necessary to provide separate bus wirings for each memory. Therefore, the number of signal lines for buses 110, 111, 112 and 113 increases, which leads the problem well known in the art that the number of terminals (pin number) to be provided at the input/output ports 107A to 107D on the end of the controller 1001 significantly increases. For solving such kinds of problems, a memory control circuit having a configuration as shown in FIG. 14 can be employed.
In the memory control circuit shown in FIG. 14, a control bus 120 and a data bus 121 are shared by the RAM 114 (source voltage 2.5 V standard) and the nonvolatile memory 115 (source voltage 3.3 V standard). In order to prevent voltages higher than the allowable value from traveling the data bus 121 and applied to the RAM 114, a data signal outputted from the nonvolatile memory 115 is converted into a signal conforming to the low voltage standard for the RAM 114 at a level converter 123 and then outputted to the data bus 121.
The controller 1002 described above includes a PAD circuit 105 conforming to the low voltage standard of the RAM 114, a CPU 101 and a memory interface 102. When accessing the memories 114 and 115, as is the same with the operation of the controller 1001 shown in FIG. 13, the CPU 101 first issues an access request with respect to the MIU 102. After approving the access request, the MIU 102 fetches an address signal AD0 and a control signal CT0 transferred from the CPU 101 and outputs them as an address signal ADin and a control signal CTin in predetermined timing.
At the PAD circuit 105, the level converter 105A converts the voltage levels of the input signals ADin and CTin and outputs signals after conversion to the control bus 120 via the output port 107A for supplying to the memories 114 and 115. In accessing the RAM 114 for writing, the level converter 105B converts the level of the data DO transferred from the CPU 101 and outputs a signal after conversion to the data bus 121 via the input/output port 107B for supplying to the RAM 114. On the other hand, when accessing the RAM 114 for reading, a data signal MD read out from the RAM 114 is transferred to the input port 107B via the data bus 121, converted to readout data DI at the level converter 105B and then inputted to the CPU 101.
In the period during which the nonvolatile memory 115 is accessed for reading, the memory controller 103 supplies an AND gate (logical product element) 122 with an output enable signal OE and a chip select signal CS which are both at high level, and the AND gate 122 supplies the level converter 123 with an approval signal of high level. The level converter 123 converts the level of the data signal read out from the nonvolatile memory 115 and inputting thereto and outputs the resultant data signal to the data bus 121 just in the period during which it receives the approval signal.
Although the memory control circuit shown in FIG. 14 and described above solves the problems associated with the memory control circuit shown in FIG. 13, it is necessary to dispose the level converter 123. There is still a problem that this level converter 123 causes increase in power consumption and decrease in operation speed of the data bus 121.
It is an object of the present invention to provide a memory control circuit and a memory control system which are capable of controlling a plurality of memories conforming to different source voltage standards from each other with low power consumption, and reducing the number of signal lines disposed between a controller and these memories, while realizing stable operation.
According to a first aspect of the present invention, a memory control circuit controls a plurality of memories having logic interfaces corresponding to different source voltages from each other, which includes a control bus, a first data bus, a second data bus and a controller. The control bus includes signal lines for transmitting an address signal and a control signal to and from a low voltage memory which operates at the minimum source voltage among the plurality of memories. The first data bus includes signal lines for transmitting data signals to and from the low voltage memory. The second data bus includes signal lines for transmitting data signals to and from a high voltage memory operating at a source voltage higher than the source voltage of the low voltage memory among the plurality of memories, and disposed independently from the first data bus. The controller accesses the low voltage memory and the high voltage memory via the control bus, first data bus and second data bus. The control bus has signal lines which branch off the signal lines of the control bus to be connected to the high voltage memory and transmit an address signal and a control signal to the high voltage memory.
According to the first aspect of the present invention, an address signal and a control signal supplied to the low voltage memory and the high voltage memory are transmitted via the common control bus. Therefore, the number of signal lines of the control bus can be reduced, and the number of pins for data input/output at the controller can be reduced. In addition, since the number of signal lines of the control bus is small, power consumption at the memory control circuit can be reduced. Furthermore, since the address signal and the control signal are transmitted at a voltage level in conformance with the logic interface of low voltage level, a voltage exceeding the acceptable level will not be applied to the low voltage memory, resulting that both the low voltage memory and the high voltage memory can be operated in a stable manner.
According to a second aspect of the present invention, in the memory control circuit according to the first aspect of the present invention, the controller includes first to third level converters. The first level converter outputs the address signal and the control signal obtained by converting voltage levels of internal signals in accordance with the input voltage defined by the logic interface of the low voltage memory to the control bus. The second level converter converts voltage level of an input signal or an output signal in accordance with an input voltage or an output voltage defined by the logic interface of the low voltage memory, and sends/receives the data signal via the first data bus. The third level converter converts voltage level of an input signal or an output signal in accordance with an input voltage or an output voltage defined by the logic interface of the high voltage memory, and sends/receives the data signal via the second data bus.
According to a third aspect of the present invention, in the memory control circuit according to the first or second aspect of the present invention, the range of output voltages defined by the logic interface of the low voltage memory is included in a range of input voltages defined by the logic interface of the high voltage memory.
According to a fourth aspect of the present invention, in the memory control circuit according to any of the first to third aspects of the present invention, a RAM (random access memory) is used as the low voltage memory, and a nonvolatile memory is used as the high voltage memory.
According to a fifth aspect of the present invention, in the memory control circuit according to the fourth aspect of the present invention, the first data bus branches off to be connected to the high voltage memory for transmitting either one or both of the address signal and the control signal to the high voltage memory.
According to a sixth aspect of the present invention, a memory control circuit includes a controller which accesses one of a first memory group and a second memory group. The first memory group includes a plurality of memories having logic interfaces corresponding to different source voltages from each other, and the second memory group includes a plurality of memories having logic interfaces corresponding to the same source voltage as each other. The memory control circuit according to the sixth aspect of the present invention is provided with a memory control circuit according to any of the first to fifth aspects when the controller accesses the first memory group. In the memory control circuit according to the sixth aspect of the present invention, when the controller accesses the second memory group, the control bus and the first data bus in the memory control circuit according to any of the first to fifth aspects of the present invention are shared and connected with all the memories of the second memory group, and the second data bus in the memory control circuit according to any of the first to fifth aspects of the present invention is used for signal transmission other than the sending/receiving of control signal and data signal to/from the memories.
According to the sixth aspect of the present invention, when the controller accesses the second memory group, the controller can use the second data bus and the third level converter usable in accessing to the first memory group, for signal transmission other than sending/receiving of control signal and data signal to/from the memories, so that a general-purpose memory control circuit can be realized.
Next, according to a seventh aspect of the present invention, a memory control circuit can control a plurality of memories having logic interfaces supporting different source voltages from each other, and includes a control bus, a first data bus, a second data bus and a controller. The control bus includes signal lines for transmitting an address signal and a control signal to and from a main memory which operates at the minimum source voltage among the plurality of memories. The first data bus transmits a data signal to and from the main memory. The second data bus transmits a data signal which conforms to the logic interface of a boot memory operating at a higher source voltage than the source voltage of the main memory among the plurality of memories. And the controller accesses the main memory to perform activation process of the memory control circuit. In the memory control circuit according to the seventh aspect of the present invention, when the second data bus is not connected to the boot memory, the second data bus is connected to an external controller for transferring initial data required for the activation process, and the controller controls so as to store the initial data transferred from the external controller in the main memory and thereafter performs the activation process using the initial data.
According to the seventh aspect of the present invention, the second data bus provided for the boot memory can be used as a bus for transmitting the initial data required for activation process. Therefore, the memory control circuit according to the present aspect does not need to have a second boot memory since it executes a slave operation of loading initial data for activation from the external controller, with the result that reduction in substrate area as well as reduction in power consumption can be realized. In addition, since the pins connected to the second data bus can be used as functional pins dedicated for loading of initial data, another functional pins are not necessary for the slave operation, which provides an advantage that the function is not restricted.
According to an eighth aspect of the present invention, in the memory control circuit according to the seventh aspect of the present invention, the controller includes first to third level converters. The first level converter outputs to the control bus an address signal and a control signal obtained by converting voltage levels of internal signals in accordance with an input voltage defined by the logic interface of the main memory. The second level converter converts voltage level of an input signal or an output signal in accordance with an input voltage or an output voltage defined by the logic interface of the boot memory, and sends/receives the data signal via the first data bus. The third level converter converts voltage level of an input signal or an output signal in accordance with an input voltage or an output voltage defined by the logic interface of the controller, and receives the initial data via the second data bus.
According to a ninth aspect of the present invention, a control system includes a memory control circuit according to the seventh or eighth aspect of the present invention, and an external controller for transmitting initial data required for the activation process to the memory control circuit.